獵頭勿擾
Job Description:
Solid understanding of related CMOS process such as 90nm, 55nm, 40nm
IO circuit design methodology, flow, concept, and good understanding of analog circuit, ESD, and LU
Preferred experience in design and development of GPIO’s, USB
Excellent communication skills in interactions with internal R&D teams
Familiar with MCU is a plus
Responsibilities:
Circuit design including GPIO and special IO’s, layout guide, SOC project support
Qualification:
Experience required: 3+ year
Education: Bachelor/Master/PhD
薪資按照個(gè)人實(shí)際工作能力和技術(shù)水平來評定。
職位福利:五險(xiǎn)一金、年底雙薪、年終分紅、餐補(bǔ)、帶薪年假、周末雙休、定期體檢、員工旅游